Advanced Techniques for Improving Processor Performance in a Superscalar Architecture
نویسندگان
چکیده
The main aim of this short paper is to investigate multiple-instruction-issue in a high-performance superscalar architecture, illustrating the optimum values for some processing parameters, as well as some advanced techniques for improving processor performance, such as dependence collapsing and instruction bypassing. Our analysis is based on a trace driven simulation method. The simulation results are presented in terms of instructions per cycle (IPC) and we summarised them by taking the harmonic mean over the benchmark set. During the simulation we have used as a main metric the average issue rate.
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تاریخ انتشار 2000